View L6382D_2774940.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

may 2006 rev 5 1/22 22 L6382D power management unit for microcontrolled ballast general features integrated high-voltage start-up 4 drivers for pfc, half-bridge & pre-heating mosfets 3.3v microcontroller compatible fully integrate power management for all operating modes internal two point v cc regulator over-current protection with digital output signal cross-conduction protection (interlocking) under voltage lock-out integrated bootstrap diode applications dimmable / non-dimmable ballast description the L6382D is suitable for microcontrolled electronic ballasts embedding a pfc stage and a half-bridge stage. the L6382D includes 4 mosfet driving stages (for the pfc, for the half bridge, for the preheating mosfet) plus a power management unit (pmu) featuring also a reference able to supply the microcontroller in any condition. besides increasing the application efficiency, the L6382D reduces the bill of materials because different tasks (regarding drivers and power management) are performed by a single ic, which improves the application reliability. so-20 www.st.com block diagram
contents L6382D 2/22 contents 1 device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1.1 start-up mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1.2 save mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1.3 operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6.1.4 shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7 block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1 supply section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.2 3.3v reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.3 drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.4 internal logic, over current protection (ocp) and interlocking function . . 17 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
L6382D device description 3/22 1 device description designed in high-voltage bcd off-line technology, the L6382D is a pfc and ballast controller provided with 4 inputs pin and a high voltage start-up generator conceived for applications manage d by a microcontroller providing the maximum flexibility. it allows the designer to use the same ballast circuit for di fferent lamp wattage/type by simply changing the c software. the digital input pins - able to receive signals up to 400khz - are connected to level shifters that provide the control signals to their relevant drivers; in particular the L6382D embeds one driver for the pfc pre-regulator stage, two drivers for the ballast half-bridge stage (high voltage, including also the bootstrap function) and the last one to provide supplementary features like preheating of filaments supplied through isolated windings in dimmable applications. a precise reference voltage (+3.3v 1%) able to provide up to 30ma is available to supply the c: this current is obtained thanks to the on-chip high voltage start-up generator that, moreover, keeps the consumption before start-up below 150 a. the chip has been designed with advanced power management logic to minimize power losses and increase the application reliability. in the half-bridge section, a patented integrated bootstrap section replaces the external bootstrap diode. the L6382D integrates also a function that regulates the ic supply voltage (without the need of any external charge pump) and optimizes the current consumption. figure 1. typical system block diagram
pin settings L6382D 4/22 2 pin settings 2.1 pin connection figure 2. pin connection (top view) 2.2 pin description 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 pfi lsi hsi hei pfg n.c. tpr gnd lsg vcc vref csi cso heg n.c. hvsu n.c. out hsg boot 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 pfi lsi hsi hei pfg n.c. tpr gnd lsg vcc vref csi cso heg n.c. hvsu n.c. out hsg boot table 1. pin description name pin n description 1pfi digital input signal to control the pfc gate driver. this pin has to be connected to a ttl compatible signal. 2lsi digital input signal to control the half-bridge low side driver. this pin has to be connected to a ttl compatible signal. 3hsi digital input signal to control the half-bridge high side driver. this pin has to be connected to a ttl compatible signal. 4hei digital input signal to control the heg out put. this pin has to be connected to a ttl compatible signal. 5pfg pfc driver output. this pin is int ended to be connected to the pfc power mosfet gate. a resistor connected bet ween this pin and the power mos gate can be used to reduce the peak current. an internal 10k ? resistor toward ground avoids spurious and undesired mosfet turn-on. the totem pole output stage is able to drive the power mos with a peak current of 120ma source and 250ma sink. 6 n.c. not connected 7tpr input for two point regulator; by coupling the pin with a capacitor to a switching circuit, it is possible to implement a charge circuit for the vcc. 8gnd chip ground. current return for both the low-side gate-drive currents and the bias current of the ic. all of the ground connections of the bias components should be tied to a trace going to this pin and kept separate from any pulsed current return.
L6382D pin settings 5/22 9lsg low side driver output. this pin must be connected to the gate of the half- bridge low side power mosfet. a resistor connected between this pin and the power mos gate can be used to reduce the peak current. an internal 20k ? resistor toward ground avoids spurious and undesired mosfet turn-on. the totem pole output stage is able to drive power with a peak current of 120ma source and 120ma sink. 10 vcc supply voltage for the signal part of the ic and for the drivers. 11 boot high-side gate-drive floating supply voltage. the bootstrap capacitor connected between this pin and pin 13 (out) is fed by an internal synchronous bootstrap diode driven in phase with the low-side gate-drive. this patented structure normally replaces the external diode. 12 hsg high side driver output. this pin must be connected to the gate of the half bridge high side power mosfet . a resistor connected between this pin and the power mos gate can be used to reduce the peak current. an internal 20k ? resistor toward out pin avoids spurious and undesired mosfet turn-on the totem pole output stage is able to drive the power mos with a peak current of 120ma source and 120ma sink. 13 out high-side gate-drive floating ground. current return for the high-side gate-drive current. layout carefully the connection of this pin to avoid too large spikes below ground. 14 n.c. not connected 15 hvsu high-voltage start-up. the current flowing into this pin charges the capacitor connected between pin vcc and gnd to st art up the ic. whilst the chip is in save mode, the generator is cycled on-off between turn-on and save mode voltages. when the chip works in operating mode the generator is shut down and it is re-enabled when the vcc voltage falls below the uvlo threshold. according to the required v ref pin current, this pin can be connected to the rectified mains voltage either di rectly or through a resistor. 16 n.c. high-voltage spacer. the pin is not conn ected internally to isolate the high- voltage pin and comply with safety r egulations (creepage distance) on the pcb. 17 heg output for the hei block; this driver ca n be used to drive the mos employed in isolated filaments preheating. an internal 20k ? resistor toward ground avoids spurious and undesired mosfet turn-on. 18 cso output of current sense comparator, co mpatible with ttl logic signal; during operating mode, the pin is forced low whereas whenever the oc comparator is triggered (csi> 0.5v typ.) the pin latches high. 19 csi input of current sense comparator, it is enabled only during operating mode ; when the pin voltage exceeds the internal threshold, the cso pin is forced high and the half bridge drivers are disabled. it exits from this condition by either cycling the vcc below the uvlo or with lgi=hgi=low simultaneously. 20 vref voltage reference. during normal mode an internal generator provides an accurate voltage reference that can be used to supply up to 30ma (during operating mode) to an external circuit. a small film capacitor (0.22 f min.), connected between this pin and gnd is recommended to ensure the stability of the generator and to prevent noi se from affecting the reference. table 1. pin description name pin n description
maximum ratings L6382D 6/22 3 maximum ratings 3.1 absolute maximum ratings 3.2 thermal data table 2. absolute maximum ratings symbol pin parameter value unit v cc 10 ic supply voltage (icc = 20ma) self-limited v hvsu 15 high voltage start-up generator voltage range -0.3 to 600 v v boot 11 floating supply voltage -1 to v hvsu +v cc v v out 13 floating ground voltage -1 to 600 v i tpr(rms) 6 maximum tpr rms current 200 ma i tpr(pk) 6 maximum tpr peak current 600 ma v tpr 6 maximum tpr voltage (1) 1. excluding operating mode 14 v 19 csi input voltage -0.3 to 7 v 1, 2, 3, 4 logic input voltage -0.3 to 7 v 9, 12, 17 operating frequency 15 to 400 khz 5 operating frequency 15 to 600 khz tstg storage temperature -40 to +150 c tj ambient temperature operating range -40 to +125 c table 3. thermal data symbol parameter value unit r thja maximum thermal resistance junction-ambient 120 c/w
L6382D electrical characteristics 7/22 4 electrical characteristics table 4. electrical characteristcs (t j = 25c, v cc = 13v, c driver = 1nf unless otherwise specified) symbol pin parameter test condition min typ max unit supply voltage v ccon 10 turn-on voltage 13 14 15 v v ccoff 10 turn-off voltage 7.5 8.25 9.2 v v ccsm 10 save mode voltage 12.75 13.8 14.85 v vsmhys 10 save mode hysteresys 0.12 0.16 0.2 v v ref(off) 10 reference turn-off 5.7 6 6.4 v ivccon 10 start-up current 150 a ivccsm 10 save mode current consumption 190 a (1) 150 230 a ivcc 10 quiescent current in operating mode lgi = hgi = high; no load on vref. 2ma vz 10 internal zener 16.5 17 18 v high voltage start-up imss 15 maximum current v hvsu > 50v 20 ma ilss 15 leakage current off state v hvsu = 600v 40 a two point regulator (tpr) protection t pr st 10 vcc protection level operating mode 14.0 14.5 15.0 v t pr (on) 10 vcc turn-on level operating mode; a fter the first falling edge on lsg 12.5 13 13.5 v t pr (off) 10 vcc turn-off level operating mode ; after the first falling edge on lsg 12.45 12.95 13.48 v 7 output voltage on state i tpr = 200ma 2v 7 forward voltage drop diode @ 600ma forward current. 2.3 v 7 leakage current off state v tpr = 13v 5a
electrical characteristics L6382D 8/22 lsg, heg & pfg drivers v oh(ls ) 5, 9 high output voltage ilsg = ipfg = 10ma 12.5 v 17 iheg = 2.5ma v ol(ls) 5, 9 low output voltage ilsg=ipfg=10ma 0.5 v 17 iheg = 2.5ma source current capability lsg and pfg 120 ma heg 50 ma sink current capability lsg 120 ma heg 70 pfg 250 t rise rise time lsg 115 ns heg 300 ns pfg 60 ns t fall fall time lsg 75 ns heg 110 ns pfg 40 ns t delay propagation delay (input to output) lsg; high to low and low to high 300 ns heg; high to low and low to high 200 ns pfg; high to low 250 ns pfg; low to high 200 ns r b pull down resistor lsg 20 k ? heg 50 k ? pfg 10 k ? hsg driver (voltages referred to out) v oh(hs) 12 high output voltage ihsg = 10 ma 12.5 v v ol(hs) 12 low output voltage ihsg = 10 ma 0.5 v 12 sink current capability 120 ma 12 source current capability 120 ma t rise 12 rise time cload = 1nf 115 ns t fall 12 fall time cload = 1nf 75 ns table 4. electrical characteristcs (t j = 25c, v cc = 13v, c driver = 1nf unless otherwise specified)
L6382D electrical characteristics 9/22 t delay 12 propagation delay (lgi to lsg) high to low and low to high 300 ns r b 12 pull down resistor to out 20 k ? high-side floating gate-driver supply i lkboot 11 v boot pin leakage current v boot = 580v 5a i lkout 13 out pin leakage current v out = 562v 5a r ds(on) synchronous bootstrap diode on- resistance v lvg = high 150 w forward voltage drop at 10 ma forward current 2.4 v forward current at 5v forward voltage drop 20 ma v ref v ref 20 reference voltage 15ma load. 3.267 3.3 3.366 v 20 load regulation iref = -3 to +30 ma -20 2 mv 20 voltage change 15ma load; vcc = 9v to 15v 15 mv 20 v ref latched protection 2v 20 v ref clamp @3ma v cc from 0 to v ccon during start-up;vcc from v ref(off) to 0 during shut-down; v ref <2v 1.2 1.4 v i ref 20 current drive capability -3 +30 ma save mode -3 +10 ma overcurrent buffer stage v csi 19 comparator level 0.537 0.56 0.582 v i csi 19 input bias current 500 na propagation delay cso turn off to lsg low 200 ns 18 high output voltage i cso = 200 a v ref - 0.5v 18 low output voltage i cso = -150 a 0.5 v table 4. electrical characteristcs (t j = 25c, v cc = 13v, c driver = 1nf unless otherwise specified)
electrical characteristics L6382D 10/22 dim normal mode time out 70 100 130 s vref enabling drivers 3.0 v t ed time enabling drivers 10 s logic input 1 to 4 low level logic input voltage 0.8 v 1 to 4 high level logic input voltage 2.2 v lgi pull down resistor 100 k ? table 4. electrical characteristcs (t j = 25c, v cc = 13v, c driver = 1nf unless otherwise specified)
L6382D typical electrical performance 11/22 5 typical electrical performance figure 3. uvlo thresholds [v] vs. t j figure 4. v cc zener voltage [v] vs. t j figure 5. vref [v] vs. t j figure 6. overcurrent protection threshold [v] vs. t j figure 7. propagation delays [ns] high to low vs. t j figure 8. propagation delays [ns] low to high vs. t j 7 8 9 10 11 12 13 14 15 -40 -25 0 25 50 75 100 125 vcc(on) vcc(off) 14 15 16 17 18 19 20 21 -40 -25 0 25 50 75 100 12 5 14 15 16 17 18 19 20 21 -40 -25 0 25 50 75 100 12 5 3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5 -40-25 0 255075100125 3.1 3.15 3.2 3.25 3.3 3.35 3.4 3.45 3.5 -40-25 0 255075100125 500 520 540 560 580 600 -40 -25 0 25 50 75 100 125 0 50 100 150 200 250 300 -40 -25 0 25 50 75 100 125 hs ls pf 0 50 100 150 200 250 300 -40 -25 0 25 50 75 100 125 hs ls pf
application information L6382D 12/22 6 application information 6.1 power management the L6382D has two stable states (save mode and operating mode) and two additional states that manage the start-up and fault conditions ( figure 9 ): the over current protection is a parallel asynchronous process enabled when in operating mode. following paragraphs will describe each mode an d the condition necessary to shift between them. figure 9. state diagram 6.1.1 start-up mode with reference to the timing diagram of figure 11, when power is first applied to the converter, the voltage on the bulk capacitor builds up and the hv generator is enabled to operate drawing about 10ma. this current, diminished by the ic consumption (less than 150 a), charges the bypass capacitor connecte d between pin vcc and ground and makes its voltage rise almost linear. during this phase, all ic's functions are disabled except for: the current sinking circuit on vref pin that maintains low the voltage by keeping disabled the microcontroller connected to this pin; the high-voltage start-up (hvsu) that is on (conductive) to charge the external capacitor on pin vcc. as the vcc voltage reaches the start-up threshold (14v typ.) the chip starts operating and the hv generator is switched off. save mode operating mode shut down v cc >v cc(on) v cc 3v & t ed >10 s lgi low for more than 100 s start-up v cc < v cc(off) or v ref <2v v cc L6382D application information 13/22 summarizing: ? the high-voltage start-up generator is active; ?v ref is disabled with additional sinking circuit on pin v ref enabled; ? tpr is disabled; ? ocp is disabled; ? the drivers are disabled. 6.1.2 save mode this mode is entered after the vcc volt age reaches the turn-on threshold; the v ref is enabled in low current source mode to supply the c connected to it, whose wake-up required current must be less than 10ma: if no switching activity is detected at lgi input, the high voltage start-up generator cycles on-off keeping the vcc voltage between vccon and vccsm. summarizing: ? the high-voltage start-up generator is cycling; ?v ref is enabled in low source current capability (i ref 10ma); ? tpr circuit is disabled; ? ocp is disabled; ? the drivers are disabled. if the vcc voltage falls below the v ref(off) threshold, the device enters the start-up mode. 6.1.3 operating mode after 10 s in save mode and only if the voltage at v ref is higher than 3.0v, on the falling edge on the hgi input, the drivers are enabled as well as all the ic's functions; this is the mode correspondent to the proper lamp behavior. summarizing: ? hvsu is off ?v ref is enabled in high source current mode (i ref < 30ma) ? tpr circuit is enabled ? ocp is enabled ? the drivers are enabled if there is no switching activity on lgi for more than 100 s, the ic returns in save mode. 6.1.4 shut down this state permits to manage the fault conditions in operating mode and it is entered by the occurrence on one of the following conditions: 1. vcc application information L6382D 14/22 in this state the functions are: ? the hvsu generator is on ?v ref is enabled in low source current mode (i ref < 10ma) ?tpr is disabled ? ocp is disabled ? the drivers are disabled in this state if vcc reaches vccon, the device enters the save mode otherwise, if vcc L6382D application information 15/22 figure 11. timing sequences: save mode and operating mode v ccs m v r e f lg i h v s u v cc v c c on h g i 10m s tp r s w itch in g v cco f f o p e r a ti n g m o d e v ccs m v r e f lg i h v s u v cc v c c on h g i 10m s tp r s w itch in g v cco f f o p e r a ti n g m o d e
block description L6382D 16/22 7 block description 7.1 supply section puvlo ( power under voltage lock out): this block controls the power management of the L6382D ensuring the right current consumption in each operating state, the correct v ref current capability, th e driver enabling and the high-voltage start- up generator switching. during start-up the device sinks the current necessary to charge the external capacitor on pin v cc from the high voltage bus; in this st ate the other ic's functions are disabled and the current consumption of the whole ic is less than 150 a. when the voltage on v cc pin reaches vccon, the ic enters the save mode where the puvlo block controls vcc between vccon and vccsm by switching on/off the high voltage start-up generator. hvsu (high-voltage start-up generator): a 600v internal mos transistor structure controls the vcc supply voltage during start-up and save mode conditions and it reduces the power losses during operating mode by switching off the mos transistor. the transistor has a source current capability of up to 30ma. tpr (two point regulator) & pws: during normal mode, the tpr block controls the psw switch in order to regulate the ic supply voltage (v cc ) to a value in the range between tpr(on) and tpr(off) by switching on and off the psw transistor figure 10. ? vcc > tprst: the psw is switched on immediately; ? tpr(on) < vcc < tprst: the psw is s witched on at the fo llowing falling edge of lgi; ? vcc < tpr(off): the psw is switched off at the following falling edge on lgi. when the psw switch is off, the diodes build a charge pump structure so that, connecting the tpr pin to a switching voltage (through a capacitor) it is possible to supply the low voltage section of the chip without adding any further external component. the diodes and the switch are designed to withstand a current of at least 200ma rms . 7.2 3.3v reference voltage this block is used to supply the microcontroller; this source is able to supply 10ma in save mode and 30ma in operating mode; moreover, during start-up when v ref is not yet available, an additional circuit is ensures th at, even sinking 3ma, the pin voltage doesn't exceed 1.2v. the reference is available until vcc is above v ref(off) ; below that it turns off and the additional sinking circuit is enabled again.
L6382D block description 17/22 7.3 drivers lsd ( low side driver ): it consists of a level shifter fr om 3.3v logic signal (lsi) to vcc mos driving level; conceived for the half-bridge low-side power mos, it is able to source and sink 120ma (min). hsd ( level shifter and high side driver ): it consists of a level shifter from 3.3v logic signal (hgi) to the high side gate driver input up to 600v. conceived for the half-bridge high-side power mos, the hsg is able to source and sink 120ma. pfd ( power factor driver ): it consists of a level shifter from 3.3v logic signal (pfi) to vcc mos driving level: the driver is able to source 120ma from vcc to pfg (turn-on) and to sink 250ma to gnd (turn-off); it is suitable to drive the mos of the pfc pre- regulator stage. hed ( heat driver ): it consists of a level shifter from 3.3v logic signal (hei) to vcc mos driving level; the driver is able to source 30ma from vcc to heg and to sink 75ma to gnd and it is suitable for th e filament heating when they are supplied by independent winding. bootstrap circuit : it generates the supply voltage for the high side driver (hsd). a patented integrated bootstrap section replaces an external bootstrap diode. this section together with a bootstrap capacitor provides the bootstrap voltage to drive the high side power mosfet. this function is achieved using a high voltage dmos driver which is driven synchronously with the low side external power mosfet. for a safe operation, current flow between boot pin and vcc is always inhibited, even though zvs operation may not be ensured. 7.4 internal logic, over current protection (ocp) and interlocking function the dim ( digital input monitor ) block manages the input signals delivered to the drivers ensuring that they are low during the described start-up procedure; the dim block controls the L6382D behaviour during both save and operating modes. when the voltage on pin csi overcomes the internal reference of 0.5v (typ.) the block latches the fault condition: in this state the ocp block forces low both hsg and lsg signals while cso will be forced high. this conditio n remains latched until lsi and hsi are simultaneously low and csi is below 0.5v. this function is suitable to implement an over current protection or hard-switching detection by using an external sense resistor. as the voltage on pin csi can go negative, the current must be limited below 2ma by external components. another feature of the dim block is the internal interlocking that avoids cross-conduction in the half-bridge fet's: if by chance both hgi and lgi input's are brought high at the same time, then lsg and hsg are forced low as l ong as this critical condition persists.
package mechanical data L6382D 18/22 8 package mechanical data in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second level interconnect . the category of second level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com
L6382D package mechanical data 19/22 table 5. so-20 mechanical data dim. mm. inch min typ max min typ max a 2.35 2.65 0.093 0.104 a1 0.10 0.30 0.004 0.012 b 0.33 0.51 0.013 0.200 c 0.23 0.32 0.009 0.013 d (1) 12.60 13.00 0.496 0.512 e 7.40 7.60 0.291 0.299 e 1.27 0.050 h 10.0 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 l 0.40 1.27 0.016 0.050 k 0 (min.), 8 (max.) ddd 0.10 0.004 figure 12. package dimensions
order codes L6382D 20/22 9 order codes table 6. order codes part number package packaging L6382D so-20 tube L6382Dtr so-20 tape & reel
L6382D revision history 21/22 10 revision history table 7. revision history date revision changes 15-nov-2004 1 first issue 03-jan-2005 2 changed from ?preliminary data? to ?final datasheet? 23-oct-2005 3 many modified 19-apr-2006 4 new template 22-may-2006 5 typo error in block diagram, updated values in electrical charcteristics ta b l e 4 .
L6382D 22/22 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorize representative of st, st products are not designed, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems, where failure or malfunction may result in personal injury, death, or severe property or environmental damage. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2006 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of L6382D

	To Download L6382D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .